ADM1034
http://onsemi.com
17
temperature sensor and the part. The effect of any filter
resistance seen in series with the remote sensor is
automatically cancelled from the temperature.
The construction of a filter allows the ADM1034 and the
remote temperature sensor to operate in noisy environments.
Figure 29 shows a low-pass RCR filter with the following
values: R = 100 W and C = 1 nF. This filtering reduces both
common-mode noise and differential noise.
Figure 29. Filter between Remote Sensor
and ADM1034
100 W
100 W
1 nF
D+
D
REMOTE
TEMPERATURE
SENSOR
Limits, Status Registers, and Interrupts
High and low limits are associated with each measurement
channel on the ADM1034. These can form the basis of system
status monitoring. A status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBusALERT
s can be generated to flag a processor or
microcontroller of an out-of-limit condition.
8-bit Limits
The following is a list of all the 8-bit limits on the
ADM1034:
Table 15. TEMPERATURE LIMIT REGISTERS
Register
Description
Default
0x0B
Local High Limit
0x8B (75癈)
0x0C
Local Low Limit
0x54 (20癈)
0x0D
Local THERM
Limit
0x95 (85癈)
0x0E
Remote 1 High Limit
0x8B (75癈)
0x0F
Remote 1 Low Limit
0x54 (20癈)
0x10
Remote 1 THERM
Limit
0x95 (85癈)
0x11
Remote 2 High Limit
0x8B (75癈)
0x12
Remote 2 Low Limit
0x54 (20癈)
0x13
Remote 2 THERM
Limit
0x95 (85癈)
Table 16. THERM
LIMIT REGISTERS
Register
Description
Default
0x19
THERM
% Limit
0xFF default
Out-of-Limit Comparisons
The ADM1034 measures all parameters in a round-robin
format and sets the appropriate status bit for out-of-limit
conditions. Comparisons are made differently, depending
on whether the measured value is compared to a high or low
limit.
High Limit: ?Comparison Performed
Low Limit: < Comparison Performed
Analog Monitoring Cycle Time
The analog monitoring cycle time begins on powerup, or,
if monitoring has been disabled, by writing a 1 to the
monitor/STBY bit of Configuration Register 1,
(Address 0x01). The ADC measures each one of the analog
inputs in turn; as each measurement is completed, the result
is automatically stored in the appropriate value register. The
round-robin monitoring cycle continues unless it is disabled
by writing a 0 to the monitor/STBY bit (Bit 0) of
Configuration Register 1 (Address 0x01).
The ADC performs round-robin conversions and takes
11 ms for the local temperature measurement and 32 ms for
each remote temperature measurement with averaging
enabled.
The total monitoring cycle time for the average
temperatures is therefore nominally
(2 32) ) 11 + 75 ms
(eq. 2)
Once the conversion time elapses, the round robin starts
again. For more information, refer to the Conversion Rate
Register section.
Fan TACH measurements take place in parallel and are
not synchronized with the temperature measurements in any
way.
Status Registers
The results of limit comparisons are stored in the status
registers. A 1 represents an out-of-limit measurement; a 0
represents an in-limit measurement. The status registers are
located at Addresses 0x4F to 0x51.
If the measurement is outside its limits, the corresponding
status register bit is set to 1. It remains set at 1 until the
measurement falls back within its limits and it is read or until
an ARA is completed.
Poll the state of the various measurements by reading the
status registers over the serial bus. If Bit 0 (ALERT
low) of
Status Register 3 (Address 0x51) is set, this means that the
ALERT
output has been pulled low by the ADM1034.
Pin 14 can be configured as a SMBusALERT
output. This
automatically notifies the system supervisor of an
out-of-limit condition. Reading the status register clears the
status bit as long as the error condition is gone.
Status register bits are sticky. Whenever a status bit is set
due to an out-of-limit condition, it remains set even after the
triggering event has gone. The only way to clear the status
bit is to read the status register (after the event has gone).
Interrupt mask registers (Reg. 0x08, Reg. 0x09, Reg. 0x0A)
allow individual interrupt sources to be masked from
causing an ALERT
. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is
set in the status register.
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